From a70a247ef1e894dfc0e86c82cf26032f1944690a Mon Sep 17 00:00:00 2001 From: minjaesong Date: Wed, 22 Nov 2023 17:08:07 +0900 Subject: [PATCH] more on the verum-nimply logic --- work_files/verum-nimply_logic.md | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/work_files/verum-nimply_logic.md b/work_files/verum-nimply_logic.md index ff39d89a6..b84729e11 100644 --- a/work_files/verum-nimply_logic.md +++ b/work_files/verum-nimply_logic.md @@ -10,7 +10,7 @@ Verum is a logic-gate modelling of the "Signal Source". | 1 | ### Falsum (⊥) -Verum is a logic-gate modelling of the "Lack of Signal" or "No Connection". +Falsum is a logic-gate modelling of the "Lack of Signal" or "No Connection". | Output | |----| | 0 | @@ -47,8 +47,13 @@ This document will use the convention where the Collector is placed on the lefth = (⊤ ↛ (p ↛ (⊤ ↛ q))) ### p OR q -= NOT ( NOT(p) AND NOT(q) ) -= NOT ( (⊤ ↛ p) AND (⊤ ↛ q) ) -= NOT ( ( (⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ p)) ) ) -= (⊤ ↛ ( ( (⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ p)) ) )) +Method 1: += NOT (NOT(p) AND NOT(q)) += NOT ((⊤ ↛ p) AND (⊤ ↛ q)) += NOT ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q))) += (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q)))) +Method 2: += (NOT p) NAND (NOT q) += (⊤ ↛ ((NOT p) ↛ (⊤ ↛ (NOT p)))) += (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q)))) Note: For the most cases, an OR gate can be substituted using merging wires and diodes.