mirror of
https://github.com/curioustorvald/tsvm.git
synced 2026-03-07 19:51:51 +09:00
mon: better support for negative address
This commit is contained in:
@@ -38,6 +38,13 @@ let peek = (p) => {
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}
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}
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}
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}
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let printAddr = (P) => {
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if (P >= 0)
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print(' $'+(uhex(P, 6))+' : ')
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else
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print('-$'+(uhex(-P, 6))+' : ')
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}
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while (1) {
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while (1) {
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print(prompt[+!pE])
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print(prompt[+!pE])
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let buf = read().split(' ')
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let buf = read().split(' ')
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@@ -50,13 +57,15 @@ while (1) {
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let addr = parseInt(buf[1], 16)
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let addr = parseInt(buf[1], 16)
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let addr2 = parseInt(buf[2], 16)
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let addr2 = parseInt(buf[2], 16)
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if (Number.isNaN(addr)) {
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if (Number.isNaN(addr)) {
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println((uhex(P, 6))+' : '+uhex(peek(P)))
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printAddr(P)
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println(uhex(peek(P)))
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pE = undefined
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pE = undefined
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}
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}
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else {
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else {
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let oldP = P
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let oldP = P
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P = addr
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P = addr
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if (Number.isNaN(addr2)) {
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if (Number.isNaN(addr2)) {
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printAddr(P)
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println(uhex(peek(P)))
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println(uhex(peek(P)))
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pE = undefined
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pE = undefined
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}
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}
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@@ -65,7 +74,7 @@ while (1) {
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else {
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else {
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for (let i = 0; i <= Math.abs(addr2) - Math.abs(addr); i++) {
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for (let i = 0; i <= Math.abs(addr2) - Math.abs(addr); i++) {
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if (i % 16 == 0 && i > 0) { println() }
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if (i % 16 == 0 && i > 0) { println() }
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if (i % 16 == 0) { print((uhex(P, 6))+' : ') }
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if (i % 16 == 0) { printAddr(P) }
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print(uhex(peek(P)) + ' ')
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print(uhex(peek(P)) + ' ')
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if (addr < 0 && addr2 < 0) { P-- } else { P++ }
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if (addr < 0 && addr2 < 0) { P-- } else { P++ }
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}
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}
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@@ -77,7 +86,8 @@ while (1) {
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}
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}
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else if ("N" == cmd) {
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else if ("N" == cmd) {
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if (P >= 0) { P++ } else { P-- }
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if (P >= 0) { P++ } else { P-- }
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println((uhex(P, 6))+' : '+uhex(peek(P)))
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printAddr(P)
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println(uhex(peek(P)))
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pE = undefined
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pE = undefined
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}
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}
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else if ("J" == cmd) {
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else if ("J" == cmd) {
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@@ -90,7 +100,12 @@ while (1) {
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}
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}
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}
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}
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else if ("P" == cmd) {
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else if ("P" == cmd) {
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if (P >= 0) {
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println(` ${P} ($${uhex(P, 6)})`)
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println(` ${P} ($${uhex(P, 6)})`)
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}
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else {
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println(` ${P} (-$${uhex(-P, 6)})`)
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}
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pE = undefined
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pE = undefined
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}
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}
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else if ("W" == cmd) {
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else if ("W" == cmd) {
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@@ -86,6 +86,9 @@ MMIO
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80..87 RO: RTC in microseconds
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80..87 RO: RTC in microseconds
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88 RW: Rom mapping
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88 RW: Rom mapping
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write 0xFF to NOT map any rom
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write 0x00 to map BIOS
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write 0x01 to map first "extra ROM"
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89 RW: BMS flags
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89 RW: BMS flags
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0b P000 b0ca
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0b P000 b0ca
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@@ -103,6 +106,10 @@ MMIO
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90 RO: BMS calculated battery percentage where 255 is 100%
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90 RO: BMS calculated battery percentage where 255 is 100%
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91 RO: BMS battery voltage multiplied by 10 (127 = "12.7 V")
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91 RO: BMS battery voltage multiplied by 10 (127 = "12.7 V")
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92 RW: Memory Mapping
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0: 8 MB Core, 8 MB Hardware-reserved, 7 card slots
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1: 12 MB Core, 4 MB Hardware-reserved, 3 card slots (HW addr 131072..1048575 cannot be reclaimed though)
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1024..2047 RW: Reserved for integrated peripherals (e.g. built-in status display)
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1024..2047 RW: Reserved for integrated peripherals (e.g. built-in status display)
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2048..4075 RW: Used by the hypervisor
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2048..4075 RW: Used by the hypervisor
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@@ -260,7 +267,7 @@ SPRITE FORMAT DRAFT 2
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0b 0000 00vp
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0b 0000 00vp
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(p: 0 for above-all, 1 for below-text, v: show/hide)
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(p: 0 for above-all, 1 for below-text, v: show/hide)
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3 bytes
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3 bytes
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Pointer to raw pixmap data in Scratchpad Memory
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Pointer to raw pixmap data in Core Memory
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MMIO
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MMIO
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@@ -809,11 +816,11 @@ MMIO
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0 RW : Bank number for the first 512 kbytes
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0 RW : Bank number for the first 512 kbytes
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1 RW : Bank number for the last 512 kbytes
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1 RW : Bank number for the last 512 kbytes
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16..23 RW : DMA Control for Lane 1..8
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16..23 RW : DMA Control for Lane 1..8
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Write 0x01: copy from Scratchpad to Peripheral
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Write 0x01: copy from Core to Peripheral
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Write 0x02: copy from Peripleral to Scratchpad
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Write 0x02: copy from Peripheral to Core
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* NOTE: after the transfer, the bank numbers will revert to the value that was befer the operation
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* NOTE: after the transfer, the bank numbers will revert to the value that was before the operation
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24..31 RW : DMA Control reserved
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24..31 RW : DMA Control reserved
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32..34 RW : DMA Lane 1 -- Addr on the Scratchpad Memory
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32..34 RW : DMA Lane 1 -- Addr on the Core Memory
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35..37 RW : DMA Lane 1 -- Addr on the Peripheral's Memory (addr can be across-the-bank)
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35..37 RW : DMA Lane 1 -- Addr on the Peripheral's Memory (addr can be across-the-bank)
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38..40 RW : DMA Lane 1 -- Transfer Length
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38..40 RW : DMA Lane 1 -- Transfer Length
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41..42 RW : DMA Lane 1 -- First/Last Bank Number
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41..42 RW : DMA Lane 1 -- First/Last Bank Number
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