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more on the verum-nimply logic

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minjaesong
2023-11-22 17:46:48 +09:00
parent a70a247ef1
commit 660e492035
1 changed files with 12 additions and 4 deletions
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work_files/verum-nimply_logic.md
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@@ -31,8 +31,13 @@ This document will use the convention where the Collector is placed on the lefth
## Derivations
### Diode
= (p ↛ ⊥)
### Falsum
⊥ = (⊤ ↛ ⊤)
### Buffer
p = (p ↛ ⊥)
= NOT (NOT p)
= (⊤ ↛ (⊤ ↛ p))
### NOT p
= (⊤ ↛ p)
@@ -43,6 +48,7 @@ This document will use the convention where the Collector is placed on the lefth
### p NAND q
= NOT (p AND q)
= NOT (p ↛ (NOT q))
= NOT (p ↛ (⊤ ↛ q))
= (⊤ ↛ (p ↛ (⊤ ↛ q)))
@@ -51,9 +57,11 @@ Method 1:
= NOT (NOT(p) AND NOT(q))
= NOT ((⊤ ↛ p) AND (⊤ ↛ q))
= NOT ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q)))
= (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q))))
= NOT ((⊤ ↛ p) ↛ q)
= (⊤ ↛ ((⊤ ↛ p) ↛ q))
Method 2:
= (NOT p) NAND (NOT q)
= (⊤ ↛ ((NOT p) ↛ (⊤ ↛ (NOT p))))
= (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q))))
Note: For the most cases, an OR gate can be substituted using merging wires and diodes.
= (⊤ ↛ ((⊤ ↛ p) ↛ q))
Note: For the most cases, an OR gate can be substituted using merging wires and buffers.