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more on the verum-nimply logic

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minjaesong
2023-11-22 17:08:07 +09:00
parent bcd1b5c0c1
commit a70a247ef1
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work_files/verum-nimply_logic.md
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@@ -10,7 +10,7 @@ Verum is a logic-gate modelling of the "Signal Source".
| 1 |
### Falsum (⊥)
Verum is a logic-gate modelling of the "Lack of Signal" or "No Connection".
Falsum is a logic-gate modelling of the "Lack of Signal" or "No Connection".
| Output |
|----|
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@@ -47,8 +47,13 @@ This document will use the convention where the Collector is placed on the lefth
= (⊤ ↛ (p ↛ (⊤ ↛ q)))
### p OR q
= NOT ( NOT(p) AND NOT(q) )
= NOT ( (⊤ ↛ p) AND (⊤ ↛ q) )
= NOT ( ( (⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ p)) ) )
= (⊤ ↛ ( ( (⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ p)) ) ))
Method 1:
= NOT (NOT(p) AND NOT(q))
= NOT ((⊤ ↛ p) AND (⊤ ↛ q))
= NOT ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q)))
= (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q))))
Method 2:
= (NOT p) NAND (NOT q)
= (⊤ ↛ ((NOT p) ↛ (⊤ ↛ (NOT p))))
= (⊤ ↛ ((⊤ ↛ p) ↛ (⊤ ↛ (⊤ ↛ q))))
Note: For the most cases, an OR gate can be substituted using merging wires and diodes.